1. Field of the Invention
This invention relates generally to semiconductor processing, and more particularly to structures and methods for testing areas of a semiconductor chip.
2. Description of the Related Art
Scanning probe microscopy is an umbrella term that covers several scanning techniques used to diagnose semiconductor chips, such as, conducting atomic force microscopy, scanning spreading resistance microscopy, scanning capacitance microscopy and scanning tunneling microscopy. These techniques are frequently used to perform diagnostic tests on semiconductor chips, particularly, though not exclusively, after a semiconductor chip has been fabricated and subsequently deprocessed in order to expose circuit structures or other areas of interest that are slated for diagnostic examination. One requirement shared by most scanning probe microscopy techniques is a conducting pathway between a probe tip and a source of bias or voltage through the chip. In bulk semiconductor devices, the establishment of the requisite conducting pathway is a relatively straight forward matter of attaching a conductor to the bulk semiconductor side of the chip and touching or bringing the probe tip in close proximity to an area of interest of the opposite side of the chip. However, the situation is more complex in semiconductor-on-insulator dice, particularly for certain types of p-channel devices thereof. The difficulty stems from the fact that in many conventional semiconductor-on-insulator designs with p-channel devices, isolation structures are used to isolate one or perhaps a few p-channel devices from adjacent devices. These isolation structures then form laterally impenetrable barriers to conductive pathways that would ordinarily be used for SPM analysis.
One conventional technique for performing SPM analysis on a semiconductor-on-insulator chip involves the formation of a via through the front side of the semiconductor chip. In this regard, the semiconductor chip is deprocessed down to the active device layer and a deep trench is formed through the active device layer and penetrating the buried insulating layer and in a certain distance into the base semiconductor layer. This conventional technique provides a somewhat manageable system for performing SPM analysis in a n-channel area that is not radically segregated by isolation structures. However, even in such relatively open n-channel areas, this conventional technique suffers from a drawback associated with a somewhat unpredictable sheet resistance that is a function of the distance from the area of interest that the probe tip is contacting to the position of the conducting via through the front side of the chip.
A more difficult problem is associated with p-channel active areas in a semiconductor-on-insulator chip. In these circumstances, a conducting via formed through the front side of the chip may yield information only on an extremely small portion of the chip that is within a particular semiconductor device active island circumscribed by an isolation structure. It may even prove difficult to fabricate diagnostic via without destructively altering the p-channel region.
The present invention is directed to overcoming or reducing the effects of one or more of the foregoing disadvantages.